This invention relates to metal-oxide-silicon field-effect transistors (MOSFETs) and in particular vertical MOSFETs in which the gate is formed in a trench.
It is known to fabricate vertical MOSFETs in which the gate is formed in a trench. Such devices are sometimes referred to as TrenchFETs, UMOSFETs or trench-gated double-diffused MOSFETs (DMOSFETs). Trench-gated DMOSFETs are generally preferred to planar DMOSFETs because they can be formed with a higher cell packing density and therefore have a lower on-resistance.
There are, however, some disadvantages to trench-gated DMOSFETs. Having the gate positioned in a trench which extends downward into the drain tends to increase the capacitance between the gate and the drain for a given gate oxide thickness. This higher gate-to-drain capacitance reduces the switching speed of the device and this can be a problem in, for example, pulse width modulation applications. Second, when the device is required to block a reverse voltage, the electric field reaches a high level at the corners of the trench. This may create impact ionization and the consequent injection of hot carriers into the gate oxide. As a result, the gate oxide layer can be damaged leading to premature failure of the device.
These problems are becoming all the more significant because MOSFETs are being required to operate at lower and lower supply voltages. This requires that the MOSFETs turn on at lower threshold voltages. The threshold voltage is determined by the following equation:                               V          T                =                              V            FB                    +                                    1                              C                OX                                      ⁢                          Q              B                                +                      φ            S                                              (        1        )            
where VT is the threshold voltage, VFB is the flat band voltage, COX is the gate-drain capacitance across the gate oxide, QB is the bulk charge, and Fs is the surface potential. COX in turn can be expressed as:                               C          OX                =                              ϵ            OX                                t            OX                                              (        2        )            
where xcex5OX represents the permittivity of the gate oxide and tOX represents the thickness of the gate oxide layer. Thus reducing tOX reduces VT but at the cost of increasing COX.
Attempts have been made to solve these problems by increasing the thickness of the gate oxide layer at the bottom of the trench. A thick bottom oxide, however, weakens the accumulation layer that forms along the trench wall and thereby increases the on-resistance of the MOSFET.
The threshold voltage of a vertical trench-gated MOSFET is lowered by implanting cesium into the gate oxide layer. The cesium implant produces a positive charge which reduces the flat band voltage (VFB in equation (1) above). This techique is particularly useful when used in MOSFETs that have a thicker bottom gate oxide. The cesium in the bottom oxide acts as a positive charge which improves the accumulation region and thereby lowers the on-resistance of the device.